Inverted pyramid-based PERC solar cell with 21.4% efficiency
A Chinese research group has developed a PERC cell on a commercial 180-μm-thick monocrystalline silicon wafer with a standard size of 156 × 156 mm2. The cell has an open-circuit voltage (VOC) of 0.677 V, a short short-circuit current (ISC) of 9.63 A, and a fill factor of 80.30%.
Researchers from China’s Jiangsu Ocean University and Chinese PV module manufacturer Risen Solar Technology have claimed that they have achieved an efficiency of 21.4% for a passivated emitter rear contact (PERC) solar cell by using high-uniform silicon inverted pyramid (IP) structures.
IPs are light-trapping structures that are known to have superior antireflection qualities. They can be easily fabricated on single-crystalline Si wafers by irradiating the surface with a nanosecond-pulsed laser. Similar structures have the advantage of undergoing three or more bounces before being reflected away, which means one or two more bounces compared to upright pyramids.
In the past, researchers have achieved efficiencies ranging from 18.62% to 20.19% for similar solar cells. But in the latest Chinese experiment, the scientists applied the IP structures on a commercial 180-μm-thick monocrystalline silicon wafer with a standard size of 156 mm2 × 156 mm2 via metal-assisted chemical etching (MACE) and an alkali anisotropic etching technique, which they claim are compatible with existing production lines. The cell emitter was passivated through plasma-enhanced chemical vapor deposition (PECVD) with stack silicon oxide/silicon nitride (SiO2/SiNx) layers.
“Stack dielectric layers are designed to optimize the optical properties of long-wavelength by increasing inner rear reflectance while maintaining a good electrical passivation effect,” the researchers explained, noting that the layers were then combined with the stack aluminum-oxide/silicon nitride (Al2O3/SiNx) passivation of the rear surface.
In addition to the aforementioned record efficiency, the cell is also said to have shown an open-circuit voltage (VOC) of 0.677 V, a short short-circuit current (ISC) of 9.63 A, and a fill factor of 80.30%.
“The key to high performance lies in the optical superiority of the IP textures and the reduced electrical losses by the simultaneous passivation of Si IP-based n+ emitter and rear surface,” the academics said. “This novel Si IP-based PERC device structure and technique show a great potential in mass production of high-efficiency silicon-based solar cell.”
